The present invention relates to a testing circuit provided in a digital logic circuit for testing itself.
In a digital logic circuit such as an LSI, it is important to test whether its operation is normal or not. The test is usually carried out for analyzing a possible trouble occurred in the circuit, or for determining upon shipping whether it is good or not.
Testing of the digital logic circuit, in general, is carried out by entering a test pattern from the outside, and a resulting output pattern is analyzed to test the circuit.
In such tests, in particular, for LSIs, one of the most simple methods for observing the conduction of the circuit is to connect the internal nodes to be observed to the pins of the package. However, the number of input and output pins of the LSI package is finite, and it is impossible to take out all the great number of internal nodes to the cutside.
Therefore, in order to increase the observability of the internal node, a scan-pass method has been considered.
FIG. 1 shows an example of a digital logic circuit including a testing circuit which comprises a first combined circuit 1 having inputs of m-bits connected to an input terminal 11 and plurality of outputs; a second combined circuit 2 having a plurality of inputs and outputs of n-bits connected to an output terminal 12; and a plurality of scan-pass registers depicted by numerals 201 to 204. The construction and function of the scan-pass register depicted by numerals 201 to 204 are similar to each other and the scan-pass register 201 will be described below with reference to FIG. 2. The scan-pass register 201 comprises a multiplexer 210 and a data-type flip-flop 211. The multiplexer 210 has three inputs connected to a test TS, a data-in DI, and a shift-in SI terminals, respectively, and an output 0. The flip-flop 211 has an input D connected to the output 0 on the multiplexer 210, a clock input connected to a clock terminal CK and a Q-output connected to a data-out DO and a shift-out SO terminals. Each of the data-in terminals DI of the scan-pass registers 201 to 204 are connected to the outputs of the combined circuit 1, and each of the data-out terminals to the inputs of the combined circuit 2.
In addition, the shift-in terminal of the first scan-pass register 201 is connected to a shift-in terminal 13 and the shift-out terminal thereof is connected to the shift-in terminal SI of the second scan-pass register 202, and this connection is repeated with the remaining scan-pass registers 202 to 203, and the shift-out terminal SO of the final stage of scan-pass register 204 is connected to a shift-out terminal 14. Also, the test terminals of scan-pass registers 201 to 204 are connected to a test terminal TS, and the clock terminals of scan-pass registers to a clock terminal 15.
The signal supplied to the terminal TS switches the scan-pass register 201 into a normal mode and the test mode. During the normal mode, the multiplexer 210 allows to pass a signal supplied to DI to the input D of the flip-flop 211 through the output 0, so that the multiplexer 210 functions as an ordinary flip-flop.
On the-other hand, during the test mode, the multiplexer 210 selects the signal on SI terminal which passes through the flip-flop 211 and then supplied to the SI terminal of the following scan-pass register 202. All the scan-pass registers perform the same function, the scan-pass registers act as a shift register. Therefore, the output on the terminal SO indicates the function of all the scan-pass registers in accordance with the timing of the clock signal on the terminal CK in a serial manner.
In the conventional testing circuit according to the scan-pass method as described above, since the internal flip-flops form a shift register during the test mode, data do not come out up to the observing point unless numerous clocks are entered, when one wants to know the status of the flip-flop of interest.
Furthermore, since, in the test mode, the internal FF operates as the shift register, execution of the program must be stopped, which lacks a real time performance.
Still further, as shown in FIG. 2, since data is entered to flip-flop via a multiplexer, some extent of delay results, which degrades the performance further than at the original maximum operating frequency of the circuit.
Accordingly, an object of the present invention is to provide a testing circuit which allows the register within the circuit to be specified in a programmable manner while allowing the value of that register to be emitted to the outside in real time without interrupting the execution of the program.